TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 53

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

5 3 o f 2 2 6
BYPRXDATA7
BYPRXDATA6
BYPRXDATA5
BYPRXDATA4
BYPRXDATA3
BYPRXDATA2
BYPRXDATA1
BYPRXDATA0
BYPRXSEQ
BYPRXCLK
Symbol
Symbol
TDO
TMS
TCK
TRS
TDI
BOUNDARY SCAN
SDH/SONET RECEIVE BYPASS INTERFACE
Lead No.
Lead No.
AA2
AA3
AA1
W5
W3
W2
A3
D6
C5
B4
B5
Y4
Y3
Y2
V4
I/O/P
I/O/P
O(T)
I
I
I
I
I
I
I
LVCMOS
- Lead Descriptions -
LVTTLp
LVTTLp
LVTTLp
LVTTLp
LVTTL
LVTTL
LVTTL
Type
Type
4mA
Test Boundary Scan Clock: This signal is used to shift
data into TDI on its rising edge and out of TDO on its
falling edge. The maximum clock frequency is 10 MHz.
Test Boundary Scan Data Input: Serial test instruc-
tions and data are clocked into this lead on the rising
edge of TCK. This lead has an internal pull-up resistor.
Test Boundary Scan Data Output: Serial test instruc-
tions and data are clocked onto this lead on the falling
edge of TCK. When inactive, this lead goes into a high
impedance state.
Test Boundary Scan Mode Select: This input lead is
sampled on the rising edge of TCK. It is used to place
the Test Access Port controller into various states, as
defined in [IEEE 1149.1].
This lead has an internal pull-up resistor.
Test Boundary Scan Reset: An active low signal that
asynchronously resets the Test Access Port controller.
The reset must be present for a minimum of 250 ns.
This lead has an internal pull-up resistor.
This lead must be tied to VSS for normal operation.
Receive Line Bypass Clock:
For TranSwitch testing purposes.
This lead must be tied to VSS.
Receive Line Bypass Sequence:
For TranSwitch testing purposes.
This lead must be tied to VSS.
Receive Line Bypass Data:
For TranSwitch testing purposes.
These leads must be tied to VSS.
Name/Function
Name/Function
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005