HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 92

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
5.6.2.3
5.6.3
5.7
5.7.1
07-Oct-2005
92
®
Table 29. Recommended JTAG Termination
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Note:
Timing parameters
Timing parameters for the CPU interface are seen in
page
Endian
The Endian of the CPU interface may be changed to allow connection of various CPUs to the
IXF1110 MAC. The Endian selection is determined by setting the Endian bit in the
($ 0x508)” on page
JTAG (Boundary Scan)
The IXF1110 MAC includes an IEEE 1149.1 boundary scan test port for board level testing. All
inputs are accessible. The BSDL file for this device is available by accessing the intel website
developer.intel.com.
TAP Interface (JTAG)
The IXF1110 MAC includess an IEEE 1149.1 compliant Test Access Port (TAP) interface used
during boundary scan testing. The interface consists of the following five pins:
TDI and TMS require external pull-up resistors to float the pins High per the IEEE 1149.1
specification. Pull-ups are recommended on TCK and TDO. For normal operation, TRST_L can be
pulled Low, permanently disabling the JTAG interface. If the JTAG interface is used, the TAP
controller must be reset as described in
returned to a logic High.
The JTAG pins must be terminated correctly for proper device operation.
Signal
TRST_L
TDO
1. TRST_L must be pulled Low to ensure proper IXF1110 MAC operation. When TRST_L is Low, the JTAG
•
•
•
•
•
interface is disabled. If the boundary scan logic is used, TRST_L must be pulsed Low after power-up to
ensure reset of the TAP controller. For more information, refer to
page 93
TDI – Serial data input
TMS – Test mode select
TCLK – TAP clock
TRST_L – Active low asynchronous reset for the TAP
TDO – Serial data output
110.
1
Intel
or the IEEE 1149.1 Boundary Scan Specification.
Description
Pull-down through 10 K
Pull-up through 10 K
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
151).
Order Number: 250210, Revision: 009
resistor
resistor
Section 5.7.2, “TAP State Machine” on page 93
Table 39, “CPU Timing Parameters” on
Section 5.7.2, “TAP State Machine” on
“CPU Interface
and
Datasheet