HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 66

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
5.2.2.9
5.2.2.10
5.2.3
5.2.3.1
5.2.3.2
07-Oct-2005
66
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Table 104, “SPI4-2 TX Synchronization ($ 0x703)” on page
The default value for DIP4_Lock is 0x20.
MaxBurst1
MaxBurst1 is an RX SPI4-2 parameter specifying the maximum number of 16 byte blocks that
may be transmitted when the associated FIFO status indicates “starving”. Bits 24 to 16 of the
SPI4-2 RX Burst Size Register specify this parameter. The default value for MaxBurst1 is 0x006,
indicating a MaxBurst1 of 96 bytes [see
page
MaxBurst2
MaxBurst2 is an RX SPI4-2 parameter specifying the maximum number of 16 byte blocks that
may be transmitted when the associated FIFO status indicates “hungry”. Bits 8 to 0 of the SPI4-2
RX Burst Size Register specify this parameter. The default value for MaxBurst2 is 0x002, indicat-
ing a MaxBurst2 of 32 bytes (see
Dynamic Phase Alignment Training Sequence (Data Path De-skew)
Training at Start-up
The SPI4-2 Specification states that on power-up or after a reset, the training sequence (as defined
in the SPI4-2 Specification) is sent indefinitely by the source side until it receives valid FIFO status
on the FIFO bus. The specification also states that it is possible for the bus de-skew to be
completed after one training sequence takes place. It is unlikely that the bus can be de-skewed in a
single training sequence because of the presence of both random and deterministic jitter. The only
way to account for the random element is to determine an average over repeated training
sequences. Since the required number of repeats is dependent on several characteristics of the
system in which the IXF1110 MAC is being used, power on training (or training following loss of
synchronization) will continue until synchronization is achieved and the calendar is provisioned.
The length of power on training will not be a fixed number of repeats.
The number of training sequence repeats could be fairly large (16, 32, or 64). If this is necessary
every time training is required, a significant use of interface bandwidth is needed just to train and
de-skew the data path. This is only done at power-up or reset for an optimal starting point interface.
After this, periodic training provides a better adjustment and a substantially lower bandwidth
overhead.
Periodic Training
A scheduled training sequence is sent at least once every pre-configured bounded interval
(DATA_MAX_T) on both the transmit and receive paths. These training sequences are used by the
receiving end of each interface for de-skewing bit arrival times on the data and control lines. The
sequence allows the receiving end to correct for relative skew difference of up to +/- 1 bit time. The
training sequence consists of one (1) idle control word followed by one or more repetitions of a 20-
word training pattern consisting of 10 (repeated) training-control words followed by 10 (repeated)
training-data words.
173].
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
Table 101, “SPI4-2 RX Burst Size ($ 0x700)” on page
Table 101, “SPI4-2 RX Burst Size ($ 0x700)” on
175, bits 7 to 0 specify this parameter.
173).
Datasheet