HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 59

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

5.2.1
Datasheet
Table 17. SPI4-2 Interface Signal Summary (Sheet 2 of 2)
Note: The system designer should be aware that the MAC Transfer Threshold Register must be set to a
Note: Data packets with frame lengths less than 64 bytes should not be transferred to the IXF1110 MAC
Data Path
Transfer of complete packets or shorter bursts is controlled by the programmed MaxBurst1 or
MaxBurst2 in conjunction with the FIFO status bus. The maximum configured payload data
transfer size must be a multiple of 16 bytes. Control words are inserted between burst transfers
only. Once a transfer begins, data words are sent uninterrupted until an end-of-packet, or until a
multiple of 16 bytes is reached as programmed in MaxBurst1 and MaxBurst2. The interval
between the end of a given transfer and the next payload control word (marking the start of another
transfer) consists of zero or more idle control words and/or training patterns.
value which exceeds the MaxBurst1 setting of the network processor or ASIC. Otherwise, a TX
FIFO under-run may result.
The minimum and maximum supported packet lengths are determined by the application. Because
the IXF1110 MAC is targeted at the Ethernet environment, the minimum frame size is 64 bytes and
the maximum frame size is 1522 bytes for VLAN packets (1518 bytes for non-VLAN packets). For
larger frames, adjust the value of the
ease of implementation, successive start-of-packets must occur not less than eight cycles apart,
where a cycle is one control or data word. The gap between shorter packets is filled with idle
control words.
unless packet padding is enabled. If this rule is disregarded, unwanted fragments may be generated
on the network at the SerDes interface.
Figure 10 on page 60
states correspond to the type of words transferred on the data path. Transitions from the “Data
Burst” state (to “Payload Control” or “Idle Control”) are possible only on the integer multiples of
TSCLK
TSTAT1, TSTAT0
RDAT[15:0]_P/N
RDCLK_P/N
RCTL_P/N
RSCLK
RSTAT1, RSTAT0
Signal Name
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
shows cycle-by-cycle behavior of the data path for valid state transitions. The
Transmit Status Clock: LVTTL clock associated with TSTAT [1:0].
Frequency is equal to one-quarter TDCLK.
Transmit FIFO Status: LVTTL lines used to carry round-robin FIFO status
information, along with associated error detection and framing.
Receive Data: Carries payload data and in-band control from the IXF1110 MAC link-
layer device.
Internally terminated differentially with 100
Receive Data Clock: Differential LVDS clock associated with RDAT[15:0] and RCTL.
Data and control lines are driven off the rising and falling edges of the clock.
Internally terminated differentially with 100
Receive Control: RCTL is High when a control word is present on RDAT[15:0].
Otherwise, RCTL is Low.
Internally terminated differentially with 100
Receive Status Clock: LVTTL clock associated with RSTAT[1:0].
Receive FIFO Status: LVTTL lines used to carry round-robin FIFO status information,
along with associated error detection and framing.
Order Number: 250210, Revision: 009
Intel
“Max Frame Size ($ Port_Index + 0x0F)” on page
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Receive
Signal Description
07-Oct-2005
135. For
59