HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 84

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
5.5.2.1
5.5.2.2
5.5.3
5.5.4
07-Oct-2005
84
®
Table 23. LED Signal Descriptions
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Note:
Mode 0
This mode selects operations compatible with the SGS Thompson M5450 Led Display Driver
Device. This device converts the serial data stream, output by the IXF1110 MAC, into 30 direct-
drive LED outputs. In this mode, the latch signal is not required. This mode is selected by setting
bit 0 of the
Mode 1
This mode selects operations compatible with TTL (74LS595) or HCMOS (74HC595) octal shift
registers. This device converts the serial data stream, output by the IXF1110 MAC, into 30 direct-
drive LED outputs. In this mode the LED DATA, LED CLK and LED LATCH signals are used.
This mode is selected by setting bit 0 of the
LED Interface Signal Description
The IXF1110 MAC LED interface consists of three output signal pins that are 2.5 V CMOS level
pads.
descriptions.
Mode 0: Detailed Operation
Please refer to the SGS Thompson M5450 datasheet for device-operation information.
The operation of the LED Interface in Mode 0 is based on a 36-bit counter loop. The data for each
LED is placed in turn on the serial data line and clocked out by the LED_CLK.
page 85
Figure 21
falling edge of the clock and is valid for almost the entire clock cycle. This ensures that the data is
valid during the rising edge of the LED_CLK, which is used to clock the data into the M5450
device.The actual data shown in
LED DATA. The 36-bit data chain is built up as follows:
LED_LATCH
Signal Name
LED_DATA
LED_CLK
Table 23, “LED Signal Descriptions”
shows the basic timing relationship and relative positioning in the data stream of each bit.
shows the 36 clocks that are output on the LED_CLK pin. The data changes on the
Intel
“LED Control ($ 0x509)”
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Designator
Ball
A20
A19
K18
Order Number: 250210, Revision: 009
LED_CLK: This signal is an output that provides a continuous clock synchronous to
the serial data stream output on the LED_DATA pin. This clock has a maximum speed
of 720 hz.
The behavior of this signal remains constant in all modes of operation.
LED_DATA: This signal provides the data, in various formats, as a serial bit stream.
The data must be valid on the rising edge of the LED_CLK signal.
In Mode 0, the data presented on this pin is TRUE (Logic 1 = High).
In Mode 1, the data presented on this pin is INVERTED (Logic 1 = Low).
LED_LATCH: This is an output pin and the signal is used only in Mode 1 as the
Latch enable for the shift register chain.
This signal is not used in Mode 0, and should be left unconnected.
Figure 21
to 0 (default).
consists of a chain of 36 bits only, 30 of which are valid
provides LED signal names, pin numbers, and
“LED Control ($ 0x509)”
Signal Description
to 1.
Figure 21 on
Datasheet