HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 89

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HFIXF1110CC.B2 Q E000

Manufacturer Part Number
HFIXF1110CC.B2 Q E000
Description
Manufacturer
Intel
Datasheet

Specifications of HFIXF1110CC.B2 Q E000

Number Of Transceivers
1
Screening Level
Commercial
Mounting
Surface Mount
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Lead Free Status / RoHS Status
Not Compliant
5.6.2
Datasheet
Figure 23. CPU Interface Inputs/Outputs
Table 28. CPU Interface Signals
Functional Description
The CPU interface is designed for a generic 32-bit asynchronous CPU bus. The bus is a 32-bit data
bus only and has an 11-bit address bus.
The IXF1110 MAC external CPU interface is asynchronous and has no clock. This allows
flexibility for CPU selection.The interface to all IXF1110 MAC registers is synchronous to 125
MHz internally.
In some applications, synchronous-to-asynchronous glue logic is required between the IXF1110
MAC and the system CPU. This glue logic must be designed so that the IXF1110 MAC Read and
Write access times are not violated. It may be possible to interface without glue logic if the CPU
can meet the timing seen in
Figure 25, “Write Timing – Asynchronous Interface” on page
Parameters” on page 110
UPX_ADD[10:0]
Internal IXF1110 MAC registers and counters are selected using the 11-bit address bus input
provided at the CPU interface. This address must be stable for the entire cycle.
UPX_ADD[10:0]
UPX_CS_L
UPX_DATA[31:0]
UPX_WR_L
UPX_RD_L
UPX_RDY_L
Name
Intel
UPX_RDY_L
UPX_WR_L
UPX_RD_L
UPX_CS_L
UPX_ADDR[10:0]
UPX_DATA[31:0]
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Input
Input
Bi_Dir
Input
Input
Output
Order Number: 250210, Revision: 009
Figure 24, “Read Timing – Asynchronous Interface” on page
Direction
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
11
32
CMOS 2.5 V
CMOS 2.5 V
CMOS 2.5 V
CMOS 2.5 V
CMOS 2.5 V
CMOS 2.5 V
Standard
91, and
CPU Interface
Address bus
Chip Select Signal
Bi-directional data bus
Write Strobe
Read Strobe
Cycle complete indicator
Table 39, “CPU Timing
Description
B3379-01
07-Oct-2005
91,
89

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