HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 102

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
6.4.1.2
6.4.1.3
6.4.1.4
6.5
6.5.1
07-Oct-2005
102
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Note:
Note:
TX SPI4-2
After reset or power-up, the TX SPI4-2 interface outputs a constant framing pattern on TSTAT until
it receives the proper SPI4-2 training pattern from the upstream SPI4-2 device. For more
information on the required training pattern, see
(Data Path De-skew)” on page
If TDCLK is applied to the IXF1110 MAC after the device has come out of reset, the system
designer must ensure the TDCLK is stable when applied. Failure to due so can result in the
IXF1110 MAC training on a non-stable clock, causing DIP4 errors and data corruption.
Once the valid training pattern is received and the IXF1110 MAC outputs a 10-port calendar on
TSAT, bit 12 of the
synchronization on the TX SPI4-2 is complete.
Ports will show a SATISFIED status on the SPI4-2 TSTAT bus until a valid link is established for
that port. To determine if a valid link is established, see
SerDes
After reset or power-up the SerDes interface will start to output idles on the TX_P/N for forced
mode operation. If Auto-Negotiation mode is required bit 5 of the
0x18)” on page 138
appropriate code words from the link partner. Refer to
information.
CPU
The CPU interface is ready for operation after power-up or reset. Through this interface, the user
can configure the device for any desired setting from the defaults. (Refer to
page 88
SerDes Power-Down Capabilities
The IXF1110 has the ability to power down the TX and RX SerDes individually on each port (see
Section 5.3, “SerDes Interface” on page
power down the SerDes ports.
These sequences must be followed to ensure a port correctly operates when brought out of a power-
down mode:
Placing the SerDes Port in Power-Down Mode
1. Disable the port(s) by de-asserting the appropriate bit(s) in the
2. Power-down
3. The SerDes port is now powered down and the TSAT Status for the port is SATISFIED
for more information.)
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
“SerDes TX and RX Power-Down Ports 0-9 ($ 0x787)”
“SPI4-2 RX Calendar ($ 0x702)” on page 174
must be set. A link is established when the RX SerDes has received the
Order Number: 250210, Revision: 009
66.
71). Use the following sequence to correctly power up and
“Dynamic Phase Alignment Training Sequence
“Fiber Operation” on page 51
“Fiber Operation” on page
“Diverse Config ($ Port_Index +
will be set. This indicates that
“Port Enable ($ 0x500)”
“CPU Interface” on
51.
for more
Datasheet