HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 67

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

5.2.3.3
5.2.4
Datasheet
Note: DATA_MAX_T may be set to zero, disabling periodic training on the interface (refer to
The initial idle control word removes dependencies of the DIP-4 in the training control words from
preceding data words. Assuming a maximum of +/- bit time alignment jitter on each line, and a
maximum of +/- bit time relative skew between lines, there are at least eight bit times when a
receiver can detect a training control word prior to de-skew. The training data word is chosen to be
orthogonal to the training control word. In the absence of bit errors in the training pattern, a
receiver should be able successfully to de-skew the data and control lines with one training pattern.
The sending side of the data path on both the transmit and receive interfaces must schedule the
training sequence at least once every DATA_MAX_T cycles.
“SPI4-2 RX Training ($ 0x701)” on page
during normal operation, and no fine-grain correction on an on-going basis is needed. This allows
the maximum possible bandwidth for data transfer. The transmit and receive interface training
sequences are scheduled independently.
Training in a Practical Implementation
The OIF Standard states that it should be possible to train and de-skew the data input in a single
training cycle. However, from the research carried out and the variances in jitter and skew due to
board layout and clock tolerance issues, some sort of averaging over several repeated training
patterns is required to reliably determine the optimal point at which to capture the incoming data.
This is true for both static alignment and dynamic phase alignment. Therefore, several training
patterns are required for an average. The more training patterns, the more accurate the average.
The de-skew circuit in the IXF1110 MAC uses dynamic phase alignment with a typical averaging
requirement of 32 training patterns required to deliver a reliable result. During power-on training,
an unlimited number of training cycles is sent by the data sourcing device. (The standard states that
training must be sourced until a calendar has been provisioned.) In the IXF1110 MAC, the de-skew
circuit waits until completion of its programmed average over the training patterns, ensuring that
the required number of good DIP-4s is seen. Only then is a calendar provisioned.
During periodic training, it is important to ensure that the training result is no less accurate than
that already used for the initial decision during power-on training. Thus, a similar number of
training cycles must be averaged over (32). This could make the overhead associated with periodic
training large if it is required to be carried out too often. We therefore recommend that periodic
training be scheduled infrequently (DATA_MAX_T = a large number) and that the number of
repetitions of training be = 32( ).
FIFO Status Channel
FIFO status information is sent periodically over the TSTAT link from the IXF1110 MAC to the
upper layer processor device, and over the RSTAT link from the upper layer processor to the
IXF1110 MAC. The status channels operate independently.
Figure 14
channel is initially in the DISABLE state and sends the “1 1” pattern repeatedly. When FIFO status
transmission is enabled, there is a transition to the SYNC state and the “1 1” framing pattern is
sent. FIFO status words are then sent according to the calendar sequence, repeating the sequence
CALENDAR_M times, followed by the DIP-2 code.
shows the operation of the FIFO status channel. The sending side of the FIFO status
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
173). This is done when a system shows very little drift
Table 102,
07-Oct-2005
67