HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 50

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
07-Oct-2005
50
®
Table 15. Valid Decodes for TXPAUSEADD[3:0]
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Note:
Note:
5.1.3.1.3
When Flow Control is enabled in the receive direction (bit 0 in the
0x12)” on page
link partner as follows:
The IXF1110 MAC response to valid received PAUSE frames is independent of the PAUSE frame
filter settings. Refer to
5.1.3.1.4
The Transmit Pause Control interface allows an external device to trigger the generation of pause
frames. The Transmit Pause Control interface is completely asynchronous. It consists of four
address signals (TXPAUSEADD[3:0]) and a strobe signal (TXPAUSEFR). The required address
for this interface operation is placed on the TXPAUSEADD[3:0] signals and the TXPAUSEFR is
pulsed High and returned Low. Refer to
and
valid decodes for the TXPAUSEADD[3:0] signals.
interface.
Flow control must be enabled in the
Control interface operation.
There are two additional decodes provided that allow the user to generate either an XOFF frame or
XON frame from all ports simultaneously.
The default pause quanta for each port is held by the
The default value of this register is 0x05E after reset is applied.
0x0
0x1
0x2
0x3
0x4
0x5
1. The IXF1110 MAC checks the entire frame to verify that it is a valid PAUSE control frame
2. If the PAUSE frame is valid, the transmit side of the IXF1110 MAC pauses for the required
3. PAUSE does not begin until completion of the frame currently being transmitted.
TXPAUSEADD[3:0]
Table 41, “Transmit Pause Control Interface Parameters” on page
addressed to the Multicast Address 01-80-C2-00-00-01 (as specified in IEEE 802.3, Annex
31B) or has a Destinations Address matching the address programmed in the
Low ($ Port_Index + 0x00)"
number of PAUSE Quanta, as specified in IEEE 802.3, Clause 31.
Intel
Response to Received PAUSE Command Frames
Transmit Pause Control Interface
®
136), the IXF1110 MAC responds to PAUSE Command frames received from the
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Transmits a PAUSE frame on every port with a pause_time = ZERO (XON)
(Cancels all previous pause commands).
Transmits a PAUSE frame on port 0 with pause_time equal to the value programmed
in the port 0
Transmits a PAUSE frame on port 1 with pause_time equal to the value programmed
in the port 1
Transmits a PAUSE frame on port 2 with pause_time equal to the value programmed
in the port 2
Transmits a PAUSE frame on port 3 with pause_time equal to the value programmed
in the port 3
Transmits a PAUSE frame on port 4 with pause_time equal to the value programmed
in the port 4
Section 5.1.2.3.5, “Filter PAUSE Packets” on page 46
Order Number: 250210, Revision: 009
“FC TX Timer Value ($ Port_Index + 0x07)"
“FC TX Timer Value ($ Port_Index + 0x07)"
“FC TX Timer Value ($ Port_Index + 0x07)"
“FC TX Timer Value ($ Port_Index + 0x07)"
“FC TX Timer Value ($ Port_Index + 0x07)"
through
“FC Enable ($ Port_Index + 0x12)”
Figure 8, “Transmit Pause Control Interface” on page 51
“Station Address High ($ Port_Index +
TX Pause Control Interface Operation
Figure 8
“FC TX Timer Value ($ Port_Index +
illustrates the transmit pause control
“FC Enable ($ Port_Index +
113.
(XOFF).
(XOFF).
(XOFF).
(XOFF).
(XOFF).
for Transmit Pause
Table 15
for additional details.
“Station Address
0x01)".
shows the
Datasheet
0x07)").