HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 178

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
07-Oct-2005
178
®
Table 110. I
Table 111. I
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Register Description: This register provides I
2
2
1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write
C Data Ports 0-9 ($ 0x79C)
C Control Ports 0-9 ($ 0x79B) (Sheet 2 of 2)
19:16
14:11
31:24
23:16
10:0
15:8
Bit
Bit
7:0
26
25
24
23
22
21
20
15
Intel
no_ack-err
I
I
Reserved
Write Complete
Reserved
Read Valid
Port Address
Select 3:0
Read/Write
Device ID
Register
Address
Reserved
Write Data
Reserved
Read_Data
2
2
CEnable
C Start
®
Name
Name
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
This bit is set to 1 when a optical module has failed
to assert an acknowledge cycle. This signal should
be used to validate the data being read. Data is only
valid if this bit is equal to zero.
Enables device wide I
I
on read.
Reserved
Write Complete is set to a 1 when the byte write
cycle has completed.
Reserved
Read Valid is set to a 1 when valid data is available
in the DataRead7:0 field.
IXF1110 port address to be accessed
0 = Write
1 = Read
Most significant 4 bits of Device ID/Address field.
Bits 10:8 define least significant 3 bits of Device ID/
Address field.
Bits 7:0 define the register address.
Reserved
Write_Data contains the data to be written during the
I
Reserved
Read_Data contains the byte received during the
last I
2
2
C Start = 1 will initiate the I
C byte write cycle.
2
C Read Cycle.
2
C Reads and Writes.
Description
Description
2
C Accesses (Enabled = 1)
2
C cycle. This bit is clear
Type
Type
CoR
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
1
1
00000000000
0x00000000
Default
Default
0x00
0x00
0x00
0x00
Datasheet
0x0
0xA
0
0
0
0
0
0
0
1