HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 5

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

6.0
7.0
Datasheet
5.8
Applications ................................................................................................................................. 96
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Electrical Specifications ........................................................................................................... 106
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
Clocks ................................................................................................................................. 94
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
Power Supply Sequencing.................................................................................................. 96
6.1.1
6.1.2
Analog Power Filtering........................................................................................................97
TX FIFO and RX FIFO Operation ....................................................................................... 97
6.3.1
6.3.2
Reset and Initialization......................................................................................................101
6.4.1
SerDes Power-Down Capabilities..................................................................................... 102
6.5.1
6.5.2
IXF1110 MAC Unused Ports ............................................................................................ 103
Optical Module Connections to the IXF1110 MAC ........................................................... 103
6.7.1
DC Specifications .............................................................................................................108
Undershoot/Overshoot Specifications .............................................................................. 109
CPU Timing Specification ................................................................................................. 110
JTAG Timing Specification ...............................................................................................112
Transmit Pause Control Timing Specifications ................................................................. 113
Optical Module Interrupt and I
System Timing Specifications ........................................................................................... 117
LED Timing Specifications ................................................................................................ 118
SerDes Timing Specification............................................................................................. 119
SPI4-2 Timing Specifications ............................................................................................ 121
TAP Interface (JTAG) ............................................................................................92
TAP State Machine ................................................................................................ 93
Instruction Register and Supported Instructions ....................................................93
ID Register ............................................................................................................. 93
Boundary Scan Register ........................................................................................ 94
Bypass Register..................................................................................................... 94
System Interface Reference Clocks.......................................................................94
5.8.1.1
5.8.1.2
SPI4-2 Receive and Transmit Data Path Clocks ................................................... 95
JTAG Clock............................................................................................................ 95
I
LED Clock .............................................................................................................. 95
Power-Up Sequence.............................................................................................. 96
Power-Down Sequence ......................................................................................... 96
TX FIFO ................................................................................................................. 98
6.3.1.1
6.3.1.2
6.3.1.3
RX FIFO............................................................................................................... 100
SPI4-2 Initialization .............................................................................................. 101
6.4.1.1
6.4.1.2
6.4.1.3
6.4.1.4
Placing the SerDes Port in Power-Down Mode ................................................... 102
Bringing the SerDes Port Out of Power-Down Mode...........................................103
SFP-to-IXF1110 Connection................................................................................ 103
2
C Clock................................................................................................................ 95
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
CLK125 .................................................................................................. 94
CLK50 .................................................................................................... 94
MAC Transfer Threshold........................................................................ 98
TX FIFO Relation to the SPI4-2 Transmit FIFO Status (TSTAT) ........... 99
TX FIFO Drain (IXF1110 Version) ......................................................... 99
RX SPI4-2 ............................................................................................ 101
TX SPI4-2 ............................................................................................ 102
SerDes ................................................................................................. 102
CPU ..................................................................................................... 102
Order Number: 250210, Revision: 009
2
C Timing Specification ..................................................... 114
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005
5