HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 12

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
07-Oct-2005
12
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IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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Intel
Globally modified SFF-8053, Revision 5.5 Compatible to SFP MSA compatible under Section 5.3,
“SerDes Interface”.
Modified Section 5.3.3, “Functional Description”.
Added Section 5.5.4.1 “Transmitter Programmable Driver-Power Levels”.
Added Table 21 “Intel
Changed Gigabit Interface Converter section to Section 5.6, “Optical Module Interface”. Globally
changed GBIC to Optical Module.
Modified Section 5.4.3.2.1, “MOD_DEF_9:0”.
Modified Section 5.6.3.2.2, “TX_FAULT_9:0”.
Modified Section 5.6.3.2.3, “RX_LOS_9:0”.
Added note to “UPX_RDY” under Section 5.8.2, “Functional Description”.
Added note under Section 6.2.1, “TX FIFO”.
Added note under Section 6.2.1.1, “MAC Transfer Threshold”.
Modified/added Power Consumption Max to Table 49 “Intel
Modified Table 36 “Intel
Added Section 7.2, “Undershoot/Overshoot Specifications”.
Modified Table 39 “Intel
Modified Table 46 “Intel
Modified Table 47 “Intel
Added caution note under Section 8.0, “Register Definitions”.
Modified Table 53 “Intel
Modified Table 65 “IPG Transmit Time Register (Addr: Port_Index + 0x0C)”.
Modified Table 66 “Pause Threshold Register (Addr: Port_Index + 0x0E)”.
Modified Table 68 “FC Enable Register (Addr: Port_Index + 0x12)”.
Modified Table 69 “Short Runts Threshold Register (Addr: Port_Index + 0x14)”.
Modified Table 71 “RX Config Word Register (Addr: Port_Index + 0x16)”.
Modified Table 72 “TX Config Word Register (Addr: Port_Index + 0x17)”.
Modified Table 73 “Diverse Config Register (Addr: Port_Index + 0x18)”.
Modified Table 74 “RX Packet Filter Control Register (Addr: Port_Index + 0x19)” (removed note 2
from bit 4, modified bit 5 description).
Modified Table 77 “MAC RX Statistics Registers (Addr: Port_Index + 0x20 - Port_Index + 0x39)”.
Added Table 81 “Core Clock Soft Reset Register (Addr: 0x504)”.
Added Table 82 “MAC Soft Reset Register (Addr: 0x505)”.
Added Table 91 “RX FIFO Port Reset Register (Addr: 0x59E)”.
Added Section 98, “TX FIFO Port Reset Register (Addr: 0x620)”.
Modified Table 100 “TX FIFO Number of Frames Removed Ports 0-9 (Addr: 0x622 - 0x62B)”.
Modified Table 103 “SPI4-2 RX Calendar Register (Addr: 0x702)”.
Modified Table 104 “SPI4-2 TX Synchronization Register (Addr: 0x703) (B0 Silicon Revision)”.
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
®
IXF1110 SerDes Driver TX Power Levels”.
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Revision Number: 005 (Sheet 2 of 3)
Revision Date: November 24, 2003
IXF1110 Receiver Characteristics” (added Common Mode Voltage Spec).
IXF1110 2.5 V LVTTL and CMOS I/O Electrical Characteristics”.
IXF1110 CPU Timing Parameters”.
IXF1110 Transmitter Characteristics”.
IXFIXF1110 Global Status and Configuration Register Map”.
Description
®
IXF1110 Operating Conditions”.
Datasheet