HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 69

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Figure 15. Example of DIP-2 Encoding
When the parity bits mimic the “1 1” pattern, the receiving end still frames successfully by syncing
onto the last cycle in a repeated “1 1” pattern, and by making use of the configured sequence length
when searching for the framing pattern.
To permit more efficient FIFO utilization, the MaxBurst1 and MaxBurst2 credits are granted and
consumed in increments of 16-byte blocks. For any given port, these credits correspond to the most
recently received FIFO status. They are not cumulative and supersede previously granted credits
for the given port. A burst transfer shorter than 16 bytes (for example, an end-of-packet fragment)
consumes an entire 16-byte credit.
A continuous stream of repeated “1 1” framing patterns indicates a disabled status link. For
example, it may be sent to indicate that the data path de-skew is not yet completed or confirmed.
When a repeated “1 1” pattern is detected, all outstanding credits are cancelled and set to zero.
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
2
3
4
5
6
7
8
9
Order Number: 250210, Revision: 009
1
1
1
0
1
0
0
0
1
0
0
a
Intel
0
1
0
0
0
0
0
0
0
1
1
b
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
DIP2 Parity Bits
to 2
to 4
to 8
to 3
to 5
to 6
to 7
to 9
(DIP2[1:0])
Framing Pattern
2nd Status Word
3rd Status Word
1st Status Word
4th Status Word
5th Status Word
6th Status Word
7th Status Word
8th Status Word
DIP2 Parity Bits
(not included
calculations)
parity in
a and b are set to 1
during enccoding
07-Oct-2005
69