HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 68

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
07-Oct-2005
68
®
Figure 14. FIFO Status State Diagram
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
The FIFO status of each port is encoded in a 2-bit data structure, which is defined in
“FIFO Status Format” on page
TSTAT[1]/RSTAT[1] and the least significant bit is sent over TSTAT[0]/RSTAT[0]. The “1 1”
pattern is reserved for In-band framing, which must be sent once prior to the start of the FIFO
status sequence.
Immediately before the “1 1” framing pattern, a DIP-2 odd parity checksum is sent at the end of
each complete sequence. The DIP-2 code is computed diagonally over TSTAT[1]/RSTAT[1] and
TSTAT[0]/RSTAT[0] for all preceding FIFO status indications sent after the last “1 1” framing
pattern, as shown in
top of the figure and the last word is at the bottom. The parity bits are computed by summing
diagonally. Bits a and b in line 9 correspond to the space occupied by the DIP-2 parity bits and are
set to 1 during encoding. The “1 1” framing pattern is not included in the parity calculation. The
procedure described applies to either parity generation on the egress path or to check parity on the
ingress path.
Intel
DIP-2
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Disable
Figure 15, “Example of DIP-2 Encoding” on page
Order Number: 250210, Revision: 009
SYNC 11
Disable
Enable
11
70. The most significant bit of each port status is sent over
Port 0
Port 5
Port 1
Port 6
Por t 2
Por t 7
69. The first word is at the
Port 3
Port 8
Port 4
Port 9
Table 20,
Datasheet