HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 173

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

8.5.7
Datasheet
Table 101. SPI4-2 RX Burst Size ($ 0x700)
Table 102. SPI4-2 RX Training ($ 0x701)
SPI4-2 Block Register Overview
Table 101
Register Description: SPI4-2 RX interface start-up parameters for burst size.
Register Description: SPI4-2 RX interface start-up parameters for training sequences
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. The value of DATA_MAX_T is the Most Significant 16 bits of a 24-bit counter value. The Least Significant 8
bits are always 0x00. This allows for a much larger DAT_MAX_T time-out period and provides a more than
adequate granularity of selection.
30:25
24:16
31:24
23:16
15:9
15:0
8:0
Bit
Bit
31
through
Intel
idles
Reserved
MaxBurst1
Reserved
MaxBurst2
Reserved
REP_T
DATA_MAX_T
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Name
Name
Table 104 on page 175
Order Number: 250210, Revision: 009
2
0 = Zero idle insertion between transfer
1 = Inserts four idle control words between
Reserved
Maximum number of 16-byte blocks that the
FIFO in the receive path, external to the
IXF1110, can accept when the FIFO Status
channel indicates STARVING.
NOTE: Do not program these bits below 0x2
Reserved
Maximum number of 16-byte blocks that the
FIFO in the receive path, external to the
IXF1110, can accept when the FIFO Status
channel indicates HUNGRY.
NOTE: Do not program these bits below 0x2
Reserved
Number of repetitions of the data training
sequence that must be scheduled every
DATA_MAX_T cycles
Maximum interval (in number of cycles)
between scheduling of training sequences on
receive data path interface
An all zero value disables periodic training
sequences.
bursts
each burst. (This occurs not only on an
EOP, but also at the end of every
MaxBurst1 or MaxBurst2.
Intel
(32 byte burst).
(32 byte burst).
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
provide an overview of the SPI4-2 Block Registers.
Description
Description
Type
Type
R/W
R/W
R/W
R/W
R/W
R
R
R
1
1
0x00060002
0x00000000
07-Oct-2005
Default
0x006
0x002
Default
0x0000
0x00
0x00
0x0
0x00
0x00
173