HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 71

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

5.2.5
5.3
5.3.1
5.3.2
Datasheet
The mechanism for both issues is the same because data will not change during a repeated period
of the same control word being transmitted on the link. If there have been some consecutive DIP-4
errors, they will be incremented towards the Loss-of-Sync threshold. This is most likely to occur
from a path requiring de-skew. If either a stream of idles or training control words follow the burst
and the DIP-4 associated with each of the words is checked, only the first one and the last one will
be seen as invalid. Any other control words in the middle will be seen as having a valid DIP-4 and
will reset the Loss-of-Sync threshold counter back to zero.
In order to avoid this, the IXF1110 MAC has altered the way in which the check is done for idle
control words and training control words. We now only validate the first occurrence of the DIP-4 in
both training control words and idle control words for correctness. We do still check each of the
words but only use the first occurrence to clear the DIP-4 error counter. Any DIP-4 error in any of
these words is still counted towards the Loss-of-Sync threshold counter. It is now impossible to
mask the DIP-4 error on our interface.
DC Parameters
For DC parameters on the SPI4-2 interface, please refer to
O Electrical Characteristics” on page 108
page
SerDes Interface
Introduction
The IXF1110 MAC has ten integrated Serializer/Deserializer (SerDes) devices that allow direct
connection to optical modules. Each SerDes interface is fully compliant with the relevant IEEE
802.3 Specifications, including auto-negotiation (see
also compliant with and supports the requirements of the Small Form Factor Pluggable (SFP)
Multi-Source Agreement (MSA), see
The following sections describe the operations supported by each SerDes interface, the
configurable options, and register bits that control these options. (A full list of the register
addresses and full bit definitions are found in the Register Map
Map” on page
Features
The SerDes cores are designed to operate in point-to-point data transmission applications. While
the core can be used across various media types, such as PCB or backplanes, it is configured
specifically for use in 1000BASE-X Ethernet fiber applications in the IXF1110. The following
features are supported.
•
•
•
•
10-bit data path, which connects to the output/input of the 8B/10B encoder/decoder PCS that
resides in the MAC controller
Data frequency of 1.25 GHz
Low power: <200 mW per SerDes port
Asynchronous clock data recovery
108.
Intel
131).
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
Intel
“Optical Module Interface” on page
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
and
Table 37, “LVDS I/O Electrical Characteristics” on
“Fiber Operation” on page
Table 36, “2.5 V LVTTL and CMOS I/
(Table 58, “SerDes Block Register
73.
51. Each port is
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