XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 97

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 3-3: PLL Ports (Continued)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Notes:
1. CLKOUT
CLKOUTDCM[0:5]
CLKOUT[0:5]
CLKFBDCM
CLKFBOUT
Pin Name
LOCKED
DO[15:0]
DI[15:0]
DRDY
DCLK
DWE
DEN
REL
N
and CLKOUTDCM
(1)
(1)
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
I/O
N
are utilizing the same output counters and can not be operated independently.
The dynamic reconfiguration data input (DI) bus provides reconfiguration data.
When not used, all bits must be set to zero.
The dynamic reconfiguration write enable (DWE) input pin provides the write
enable control signal to write the DI data into the DADDR address. When not used,
it must be tied Low.
The dynamic reconfiguration enable (DEN) provides the enable control signal to
access the dynamic reconfiguration feature. When the dynamic reconfiguration
feature is not used, DEN must be tied Low.
The DCLK signal is the reference clock for the dynamic reconfiguration port.
The release pin is used when the PLL is in PMCD mode. When in PLL mode, leave
unconnected or tied Low. Only use this pin when porting existing Virtex-4 designs
containing the legacy PMCD mode.
User configurable clock outputs (0 through 5) that can be divided versions of the
VCO phase outputs (user controllable) from 1 (bypassed) to 128. The input clock and
output clocks are phase aligned.
Dedicated PLL feedback output.
User configurable clocks (0 through 5) that can only connect to the DCM within the
same CMT as the PLL.
PLL feedback used to compensate if the PLL is driving the DCM. If the CLKFBOUT
pin is used for this purpose, the software will automatically map to the correct port.
An output from the PLL that indicates when the PLL has achieved phase alignment
within a predefined window and frequency matching within a predefined PPM
range. The PLL automatically locks after power on, no extra reset is required.
LOCKED will be deasserted if the input clock stops or the phase alignment is
violated (e.g., input clock phase shift). The PLL must be reset after LOCKED is
deasserted.
The dynamic reconfiguration output bus provides PLL data output when using
dynamic reconfiguration.
The dynamic reconfiguration ready output (DRDY) provides the response to the
DEN signal for the PLLs dynamic reconfiguration feature.
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Pin Description
General Usage Description
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