XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 194

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 5: Configurable Logic Blocks (CLBs)
194
X-Ref Target - Figure 5-20
It is possible to create shift registers longer than 128 bits across more than one SLICEM.
However, there are no direct connections between slices to form these shift registers.
Shift Register Data Flow
Shift Operation
The shift operation is a single clock-edge operation, with an active-High clock enable
feature. When enable is High, the input (D) is loaded into the first bit of the shift register.
Each bit is also shifted to the next highest bit position. In a cascadable shift register
configuration, the last bit is shifted out on the M31 output.
The bit selected by the 5-bit address port (A[4:0]) appears on the Q output.
Dynamic Read Operation
The Q output is determined by the 5-bit address. Each time a new address is applied to the
5-input address pins, the new bit position value is available on the Q output after the time
SHIFTIN (D)
A[6:0]
CLK
WE
(WE/CE)
Figure 5-20: 128-bit Shift Register Configuration
(CLK)
5
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DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
SRL32
SRL32
SRL32
SRL32
MC31
MC31
MC31
MC31
O6
O6
O6
O6
(MC31)
F7BMUX
F7AMUX
CX (A5)
AX (A5)
SHIFTOUT (Q127)
BX (A6)
F8MUX
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
D Q
(BMUX)
(BQ)
(Optional)
UG190_5_20_050506
Output (Q)
Registered
Output