XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 206

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 5: Configurable Logic Blocks (CLBs)
206
Distributed RAM Timing Characteristics
The timing characteristics of a 16-bit distributed RAM implemented in a Virtex-5 FPGA
slice (LUT configured as RAM) are shown in
X-Ref Target - Figure 5-28
Clock Event 1: Write Operation
During a Write operation, the contents of the memory at the address on the ADDR inputs
are changed. The data written to this memory location is reflected on the A/B/C/D
outputs synchronously.
•
•
•
This is also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time
T
Clock Event 2: Read Operation
All Read operations are asynchronous in distributed RAM. As long as WE is Low, the
address bus can be asserted at any time. The contents of the RAM on the address bus are
reflected on the A/B/C/D outputs after a delay of length T
a LUT). The address (F) is asserted after clock event 2, and the contents of the RAM at
address (F) are reflected at the output after a delay of length T
AX/BX/CX/DX
SHCKO
DATA_OUT
At time T
enabling the RAM for a Write operation.
At time T
inputs of the RAM.
At time T
RAM and is reflected on the A/B/C/D output at time T
A/B/C/D
A/B/C/D
(ADDR)
Output
CLK
and T
(DI)
WE
Figure 5-28: Slice Distributed RAM Timing Characteristics
AS
WS
DS
WOSCO
before clock event 1, the address (2) becomes valid at the A/B/C/D
before clock event 1, the DATA becomes valid (1) at the DI input of the
before clock event 1, the write-enable signal (WE) becomes valid-High,
1
T
WPH
1
WRITE
after clock event 1.
T
2
WC
T
T
T
AS
DS
WS
T
T
www.xilinx.com
WPL
SHCKO
1
2
X
READ
F
T
MEM(F)
ILO
3
WRITE
0
3
Figure
0
4
5-28.
WRITE
1
4
ILO
1
SHCKO
(propagation delay through
ILO
5
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
.
0
WRITE
after clock event 1.
5
0
6
X
READ
UG190_5_28_050506
E
T
ILO
MEM(E)
7