XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 184

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 5: Configurable Logic Blocks (CLBs)
184
X-Ref Target - Figure 5-8
If four single-port 64 x 1-bit modules are built, the four RAM64X1S primitives can occupy
a SLICEM, as long as they share the same clock, write enable, and shared read and write
port address inputs. This configuration equates to 64 x 4-bit single-port distributed RAM.
X-Ref Target - Figure 5-9
If two dual-port 64 x 1-bit modules are built, the two RAM64X1D primitives can occupy a
SLICEM, as long as they share the same clock, write enable, and shared read and write port
address inputs. This configuration equates to 64 x 2-bit dual-port distributed RAM.
DPRA[5:0]
WCLK
A[5:0]
WCLK
A[5:0]
WE
WE
D
D
Figure 5-8: Distributed RAM (RAM64X1S)
Figure 5-9: Distributed RAM (RAM64X1D)
6
(WE/CE)
(D[6:1])
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(CLK)
(DX)
(D[6:1])
(WE/CE)
(C[6:1])
(CLK)
6
(DX)
RAM64X1S
DI1
A[6:1]
WA[6:1]
CLK
WE
RAM64X1D
6
6
6
6
SPRAM64
DI1
A[6:1]
WA[6:1]
CLK
WE
DI1
A[6:1]
WA[6:1]
CLK
WE
DPRAM64
DPRAM64
O6
O6
O6
O
SPO
DPO
D Q
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
D Q
D Q
(Optional)
ug190_5_07_032706
Output
Registered
Output
(Optional)
(Optional)
UG190_5_09_050506
Registered
Output
Registered
Output