XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 216

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 5: Configurable Logic Blocks (CLBs)
216
Port Signals
logic in terms of performance and area. It also automatically uses and connects this
function properly.
Sum Outputs – O[3:0]
The sum outputs provide the final result of the addition/subtraction.
Carry Outputs – CO[3:0]
The carry outputs provide the carry out for each bit. A longer carry chain can be created if
CO[3] is connected to CI input of another CARRY4 primitive.
Data Inputs – DI[3:0]
The data inputs are used as “generate” signals to the carry lookahead logic. The “generate”
signals are sourced from LUT outputs.
Select Inputs – S[3:0]
The select inputs are used as “propagate” signals to the carry lookahead logic. The
“propagate” signals are sourced from LUT outputs.
Carry Initialize – CYINIT
The carry initialize input is used to select the first bit in a carry chain. The value for this pin
is either 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry bit).
Carry In – CI
The carry in input is used to cascade slices to form longer carry chain. To create a longer
carry chain, the CO[3] output of another CARRY4 is simply connected to this pin.
Figure 5-24, page 199
www.xilinx.com
illustrates the CARRY4 block diagram.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010