XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 36

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 1: Clock Resources
36
Additional Use Models
Asynchronous Mux Using BUFGCTRL
In some cases an application requires immediate switching between clock inputs or
bypassing the edge sensitivity of BUFGCTRL. An example is when one of the clock inputs
is no longer switching. If this happens, the clock output would not have the proper
switching conditions because the BUFGCTRL never detected a clock edge. This case uses
the asynchronous mux.
design example.
X-Ref Target - Figure 1-13
X-Ref Target - Figure 1-14
In
•
•
•
•
Figure
The current clock is from I0.
S is activated High.
The Clock output immediately switches to I1.
When Ignore signals are asserted High, glitch protection is disabled.
Figure 1-13: Asynchronous Mux with BUFGCTRL Design Example
1-14:
I1
I0
O
S
I1
I0
Asynchronous MUX
S
Figure 1-14
Design Example
Figure 1-14: Asynchronous Mux Timing Diagram
at I0
Figure 1-13
www.xilinx.com
shows the asynchronous mux timing diagram.
T
BCCKO_O
O
illustrates an asynchronous mux with BUFGCTRL
S
Begin I1
V
V
V
V
DD
DD
DD
DD
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
T
BCCKO_O
ug190_1_13_032306
UG190_1_14_032306
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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