XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 109

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Guidelines
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
PLL to PLL Connection
f
OUTPLL2
The PLL can be cascaded to allow generation of a greater range of clock frequencies. The
frequency range restrictions still apply.
final output frequency and the input frequency and counter settings of the two PLLs
(Figure
input clock is undefined.To cascade PLLs, route the output of the first PLL to a BUFG and
then to the CLKIN pin of the second PLL. This path provides the lowest device jitter.
X-Ref Target - Figure 3-15
This section summarizes when to select a DCM over a PLL, or a PLL over a DCM.
Virtex-5 FPGA PLLs support up to six independent outputs. Designs using several
different outputs should use PLLs. An example of designs using several different outputs
follows. The PLL is an ideal solution for this type of application because it can generate a
configurable set of outputs over a wide range while the DCM has a fixed number of
predetermined outputs based off the reference clock. When the application requires a fine
phase shift or a dynamic variable phase shift, a DCM could be a better solution.
=
IBUFG
3-15.) The phase relationship between the output clock of the second PLL and the
f
OUTPLL1
CLKIN1
CLKFBIN
RST
PLL
--------------------------------------- -
D
PLL2
M
CLKFBOUT
PLL2
×
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
www.xilinx.com
Figure 3-15: Cascading Two PLLs
O
PLL2
=
f
IN
Equation 3-9
--------------------------------------- -
D
BUFG
PLL1
M
PLL1
×
O
CLKIN1
CLKFBIN
RST
PLL1
PLL
shows the relationship between the
×
CLKFBOUT
--------------------------------------- -
D
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
PLL2
M
PLL2
Application Guidelines
×
O
PLL2
BUFG
Equation 3-9
ug190_3_16_032506
To Logic
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