XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 303

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
depending on the board design. The absolute maximum I/O limits might be exceeded
even if the clamp diode is active.
The IBIS models contain the voltage-current characteristics of the I/O drivers and clamp
diodes.
To verify overshoot and undershoot are within the I/O absolute maximum specifications,
Xilinx recommends proper I/O termination and performing IBIS simulation.
Source Termination and LVDCI_33
In general, the I/O drivers should match the board trace impedance to within ±10% to
minimize overshoot and undershoot. Source termination is often used for unidirectional
interfaces. The DCI feature has built-in source termination on all user output pins. It
compensates for impedance changes due to voltage and/or temperature fluctuations, and
can match the reference resistor values. Assuming the reference resistor values are the
same as the board trace impedance, the output impedance of the driver will closely match
with the board trace.
The LVDCI_33 standard is used to enable the DCI features for 3.3V I/O operations. As
shown in
termination function in Virtex-5 FPGA output drivers. The pull-up resistor connected to
VRN and the pull-down resistor connected to VRP determine the output impedance of all
the output drivers in the same bank. The
(DCI)
Since the LVDCI_33 standard does not offer input termination, source termination must be
implemented on the driver side.
termination resistors to be incorporated on the external device side.
The total impedance of the LVTTL/LVCMOS driver added to the series termination
resistor R
undershoot. An IBIS simulation is advised for calculating the exact value needed for R
X-Ref Target - Figure 6-92
External Device
LVTTL/
LVCMOS
Driver
Figure 6-92: Connecting LVTTL or LVCMOS Using the LVDCI_33 Standard
section has more details on using DCI.
0
Figure
must match the board trace impedance ±10 percent to minimize overshoot and
R
R
Z
6-92, the OBUF_LVDCI_33 primitive is used to implement the source
0
0
0
= 50Ω (typical)
+ R
Driver
www.xilinx.com
Z
0
=
Rules for Combining I/O Standards in the Same Bank
Figure 6-92
IBUF_LVDCI_33
Virtex-5 FPGA Digitally Controlled Impedance
Virtex-5 FPGA
OBUF_LVDCI_33
V
CCO
shows the recommended external source
= 3.3V
VRN
VRP
V
CCO
R
R
Z
REF
REF
0
Any 3.3V
I/O Device
ug190_6_86_030506
0
303
.