XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 349

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Event 1
•
•
Clock Event 4
At time T
case) becomes valid-High, resetting the output register and reflected at the OQ output at
time T
Figure 7-27
X-Ref Target - Figure 7-27
Clock Event 1
•
•
Clock Event 2
•
OCE
At time T
High at the OCE input of the output register, enabling the output register for
incoming data.
At time T
input of the output register and is reflected at the OQ output at time T
Clock Event 1.
At time T
High at the OCE input of the ODDR, enabling ODDR for incoming data. Care must be
taken to toggle the OCE signal of the ODDR register between the rising edges and
falling edges of CLK as well as meeting the register setup-time relative to both clock
edges.
At time T
valid-High at the D1 input of ODDR register and is reflected on the OQ output at time
T
At time T
valid-High at the D2 input of ODDR register and is reflected on the OQ output at time
T
CLK
OQ
SR
OCKQ
OCKQ
D1
D2
RQ
T
OCKQ
OSRCK
after Clock Event 4.
after Clock Event 1.
after Clock Event 2 (no change at the OQ output in this case).
illustrates the OLOGIC ODDR register timing.
Figure 7-27: OLOGIC ODDR Register Timing Characteristics
ODCK
OOCECK
ODCK
OOCECK
ODCK
1
before Clock Event 4, the SR signal (configured as synchronous reset in this
T
T
OOCECK
before Clock Event 2 (falling edge of CLK), the data signal D2 becomes
before Clock Event 1 (rising edge of CLK), the data signal D1 becomes
before Clock Event 1, the output signal becomes valid-High at the D1
ODCK
2
before Clock Event 1, the output clock enable signal becomes valid-
before Clock Event 1, the ODDR clock enable signal becomes valid-
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3
T
ODCK
4
5
6
T
OSRCK
7
8
9
OLOGIC Resources
10
OCKQ
T
ug190_7_22_012407
RQ
11
after
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