XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 350

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 7: SelectIO Logic Resources
350
Clock Event 9
At time T
synchronous reset in this case) becomes valid-High resetting ODDR register, reflected at
the OQ output at time T
and resetting ODDR register, reflected at the OQ output at time T
(no change at the OQ output in this case).
Figure 7-28
X-Ref Target - Figure 7-28
Clock Event 1
•
•
Clock Event 2
•
Figure 7-29
in opposite edge mode. For other modes add the appropriate latencies as shown in
Figure 7-4, page
CLK
TCE
SR
TQ
T1
At time T
High at the TCE input of the 3-state register, enabling the 3-state register for incoming
data.
At time T
input of the 3-state register, returning the pad to high-impedance at time T
Clock Event 1.
At time T
in this case) becomes valid-High, resetting the 3-state register at time T
Event 2.
OSRCK
T
OCKQ
illustrates the OLOGIC 3-state register timing.
Figure 7-28: OLOGIC 3-State Register Timing Characteristics
illustrates IOB DDR 3-state register timing. This example is shown using DDR
OTCECK
OTCK
OSRCK
before Clock Event 9 (rising edge of CLK), the SR signal (configured as
321.
1
before Clock Event 1 the 3-state signal becomes valid-High at the T
before Clock Event 2, the SR signal (configured as synchronous reset
before Clock Event 1, the 3-state clock enable signal becomes valid-
T
T
OTCK
OTCECK
RQ
www.xilinx.com
after Clock Event 9 (no change at the OQ output in this case)
2
T
OSRCK
T
RQ
3
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
RQ
after Clock Event 10
RQ
UG190_7_23_041106
5
after Clock
OCKQ
after