XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 205

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5-8: Distributed RAM Timing Parameters
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Sequential Delays for a Slice LUT Configured as RAM (Distributed RAM)
Setup and Hold Times for a Slice LUT Configured as RAM (Distributed RAM)
Clock CLK
Notes:
1. This parameters includes a LUT configured as a two-bit distributed RAM.
2. T
3. Parameter includes AI/BI/CI/DI configured as a data input (DI2).
T
T
T
T
T
T
T
ACK
SHCKO
DS
WS
WPH
WPL
WC
XXCK
/T
/T
/T
DH
WH
(1)
CKA
= Setup Time (before clock edge), and T
(3)
Parameter
Distributed RAM Timing Parameters
Table 5-8
of the paths in
shows the timing parameters for the distributed RAM in SLICEM for a majority
AX/BX/CX/DX configured as
data input (DI1)
A/B/C/D address inputs
WE input
CLK to A/B/C/D outputs
Figure
CKXX
Function
5-27.
= Hold Time (after clock edge).
www.xilinx.com
Time after the CLK of a write operation that the
data written to the distributed RAM is stable on
the A/B/C/D output of the slice.
Time before/after the clock that data must be
stable at the AX/BX/CX/DX input of the slice.
Time before/after the clock that address signals
must be stable at the A/B/C/D inputs of the slice
LUT (configured as RAM).
Time before/after the clock that the write enable
signal must be stable at the WE input of the slice
LUT (configured as RAM).
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write
cycle time.
(2)
Description
CLB / Slice Timing Models
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