SI1014-A-GM Silicon Laboratories Inc, SI1014-A-GM Datasheet - Page 78

• Manufacturer Part Number: SI1014-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1014-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 16kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1869-5

Si1010/1/2/3/4/5
5.1. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the
ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the
setting of the AD0SJST[2:0]. When the repeat count is set to 1, conversion codes are represented as 10-
bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below
for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
When the repeat count is greater than 1, the output conversion code represents the accumulated result of
the conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8,
16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0AC register. When a repeat count higher
than 1, the ADC output must be right-justified (AD0SJST = 0xx); unused bits in the ADC0H and ADC0L
registers are set to 0. The example below shows the right-justified result for various input voltages and
repeat counts. Notice that accumulating 2
samples returned from the ADC have the same value.
The AD0SJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions. Based on the principles of oversampling and averaging, the
effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4.
The example below shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12-bit, or 13-bit respectively without CPU intervention.
78
Input Voltage
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
Input Voltage
V
V
V
0
Input Voltage
V
V
V
0
REF
REF
REF
REF
REF
REF
x 1023/1024
x 512/1024
x 511/1024
x 1023/1024
x 512/1024
x 511/1024
0x0FFC
0x0800
0x0000
Shift Right = 1
11-Bit Result
0x07F7
0x0400
0x03FE
0x0000
Repeat Count = 4
0x07FC
Repeat Count = 4
Right-Justified ADC0H:ADC0L
(AD0SJST = 000)
0x03FF
0x0200
0x0100
0x0000
n
samples is equivalent to left-shifting by n bit positions when all
Repeat Count = 16
0x3FF0
0x2000
0x1FF0
0x0000
Repeat Count = 16
Shift Right = 2
12-Bit Result
0x0FFC
0x0800
0x04FC
0x0000
Rev. 1.0
Left-Justified ADC0H:ADC0L
(AD0SJST = 100)
0xFFC0
0x8000
0x4000
0x0000
Repeat Count = 64
0xFFC0
0x8000
0x7FC0
0x0000
Repeat Count = 64
Shift Right = 3
13-Bit Result
0x1FF8
0x1000
0x0FF8
0x0000