SI1014-A-GM Silicon Laboratories Inc, SI1014-A-GM Datasheet - Page 143

• Manufacturer Part Number: SI1014-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1014-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 16kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1869-5

SFR Definition 12.6. EIP2: Extended Interrupt Priority 2
SFR Page = All Pages; SFR Address = 0xF7
Name
Reset
Type
Bit
Bit
7:4
3
2
1
0
PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
PWARN Supply Monitor Early Warning Interrupt Priority Control.
Unused
PSPI1
Name
PMAT
R
7
0
Read = 0000b. Write = Don’t care.
EZRadioPRO Serial Interface (SPI1) Interrupt Priority Control.
This bit sets the priority of the SPI1 interrupt.
0: SP1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
This bit sets the priority of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: Supply Monitor Early Warning interrupt set to low priority level.
1: Supply Monitor Early Warning interrupt set to high priority level.
R
6
0
R
5
0
Rev. 1.0
R
4
0
Function
PSPI1
R/W
3
0
PRTC0F
Si1010/1/2/3/4/5
R/W
2
0
PMAT
R/W
1
0
PWARN
R/W
0
0
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