SI1014-A-GM Silicon Laboratories Inc, SI1014-A-GM Datasheet - Page 326

• Manufacturer Part Number: SI1014-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1014-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 16kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1869-5

Si1010/1/2/3/4/5
26.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
26.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is
operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant
bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
26.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is
operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-
significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and
when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire
mode, MISO is always driven by the MSB of the shift register.
26.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0
generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the
slave is not selected (NSS = 1) in 4-wire slave mode.
26.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
See Figure 26.2, Figure 26.3, and Figure 26.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “21. Port Input/Output” on page 219 for general purpose
port I/O and crossbar information.
26.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
326
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-
point communication between a master and one slave.
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
Rev. 1.0