SI1014-A-GM Silicon Laboratories Inc, SI1014-A-GM Datasheet - Page 193

• Manufacturer Part Number: SI1014-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1014-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 16kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1869-5

SFR Definition 18.2. RSTSRC: Reset Source
SFR Page = 0x0; SFR Address = 0xEF.
Notes:
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD_MCU/DC+ Supply Monitor is stabilized may generate a system reset.
WDTRSF Watchdog Timer Reset
MCDRSF Missing Clock Detector
FERROR Flash Error Reset Flag. N/A
RTC0RE SmaRTClock Reset
C0RSEF Comparator0 Reset
PINRSF
SWRSF
PORSF
Name
RTC0RE
Varies
R/W
7
Enable and Flag
Enable and Flag.
Software Reset Force
and Flag.
Flag.
(MCD) Enable and Flag.
Power-On / Power-Fail
Reset Flag, and Power-
Fail Reset Enable.
HW Pin Reset Flag.
FERROR
Varies
Description
R
6
C0RSEF
Varies
R/W
5
0: Disable SmaRTClock as a
reset source.
1: Enable SmaRTClock as a
reset source.
0: Disable Comparator0 as a
reset source.
1: Enable Comparator0 as a
reset source.
Writing a 1 forces a system
reset.
N/A
0: Disable the MCD.
1: Enable the MCD.
The MCD triggers a reset if a
missing clock condition is
detected.
0: Disable the VDD_MCU/DC+
Supply Monitor as a reset
source.
1: Enable the VDD_MCU/DC+
Supply Monitor as a reset
source.
N/A
SWRSF
Varies
R/W
Rev. 1.0
4
3
Write
WDTRSF
Varies
R
3
MCDRSF
Varies
Si1010/1/2/3/4/5
R/W
2
Set to 1 if SmaRTClock
alarm or oscillator fail
caused the last reset.
Set to 1 if Flash
read/write/erase error
caused the last reset.
Set to 1 if Comparator0
caused the last reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
Set to 1 anytime a power-on
or V
occurs.
Set to 1 if RST pin caused
the last reset.
DD
PORSF
Varies
2
monitor reset
R/W
1
Read
PINRSF
Varies
R
0
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