SI1014-A-GM Silicon Laboratories Inc, SI1014-A-GM Datasheet - Page 161

• Manufacturer Part Number: SI1014-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1014-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 16kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1869-5

14.5. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the VBAT pin (see Figure 14.1). Power to most digital logic on the
chip is disconnected; only PMU0 and the SmaRTClock remain powered. Analog peripherals remain pow-
ered in two-cell mode and lose their supply in one-cell mode because the dc-dc converter is disabled. In
two-cell mode, only the Comparators remain functional when the device enters sleep mode. All other ana-
log peripherals (ADC0, IREF0, External Oscillator, etc.) should be disabled prior to entering sleep mode.
The system clock source must be set to the low power internal oscillator or the precision oscillator prior to
entering sleep mode.
Note: When exiting Sleep Mode, 4 NOP instructions should be located immediately after the write to PMU0CF
Note: If the average active time (between successive entries into Sleep Mode) is less than 1 ms, peripherals
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode. In one-cell
mode, the VDD_MCU/DC+ supply will drop to the level of VBAT, which will reduce the output high-voltage
level and the source and sink current drive capability.
GPIO pins configured as digital inputs can be used during sleep mode as wakeup sources using the port
match feature. In two-cell mode, they will maintain the same input level specs in sleep mode as they have
in normal mode. In one-cell mode, the VDD supply will drop to the level of VBAT, which will lower the
switching threshold and increase the propagation delay.
As part of the C8051F9xx Plus feature set, a wakeup request for external devices may be generated. Upon
exit from sleep mode, the wake-up request signal is driven high, allowing other devices in the system to
wake up from their low power modes. An example of a system that may benefit from this function is one
that uses a high-power dc-dc converter (>65 mW of output power). The dc-dc converter may be disabled
when the system is asleep, and can be awoken by the wake-up request signal from the MCU. The wakeup
request signal is high when the MCU is awake and low when the MCU is asleep.
Note: By default, the VDD_MCU/DC+ supply is connected to VBAT upon entry into Sleep Mode (one-cell mode). If
RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT does not fall
below V
resume code execution upon waking up from Sleep mode. The following wake-up sources can be config-
ured to wake the device from sleep mode:
The Comparator0 Rising Edge wakeup is only valid in two-cell mode. The comparator requires a supply
voltage of at least 1.8 V to operate properly. On ‘F912 and ‘F902 devices, the VBAT supply monitor can be




SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge.
that placed the device in sleep mode. One of the two internal oscillators must be selected as the system
clock when entering Sleep Mode.
that may cause a wake-up from Sleep Mode (SmaRTClock, Port Match, and Comparator0) or are
enabled or configured in a way which may cause the wake-up flag to be set should be selected as
wake-up sources. If these peripherals are not selected as wake-up sources, then it is recommended to
bypass the Flash one-shot (FLSCL.6=1) before entering into Sleep Mode.
the VDDSLP bit (DC0CF.1) is set to logic 1, the VDD_MCU/DC+ supply will float in Sleep Mode. This allows the
decoupling capacitance on the VDD_MCU/DC+ supply to maintain the supply rail until the capacitors are
discharged. For relatively short sleep intervals, this can result in substantial power savings because the
decoupling capacitance is not continuously charged and discharged.
POR
. The PC counter and all other volatile state information is preserved allowing the device to
Rev. 1.0
Si1010/1/2/3/4/5
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