SI1014-A-GM Silicon Laboratories Inc, SI1014-A-GM Datasheet - Page 22

• Manufacturer Part Number: SI1014-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1014-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 16kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1869-5

Si1010/1/2/3/4/5
22
C2CK/RST
C2CK/RST
XTAL3
XTAL4
XTAL3
XTAL4
GND
VDD
GND
VDD
Programming
C2D
Programming
Reset/PMU
Reset/PMU
C2D
Power On
Hardware
Power On
Hardware
Debug /
Debug /
XTAL1
XTAL2
XTAL1
XTAL2
VREG
VREG
Reset
Wake
Wake
Reset
SmaRTClock
SmaRTClock
Low Power
Low Power
24.5 MHz
Precision
Oscillator
Oscillator
Oscillator
Oscillator
24.5 MHz
Precision
Oscillator
Oscillator
Oscillator
External
Oscillator
20 MHz
External
20 MHz
Controller Core
System Clock
Circuit
Configuration
Controller Core
System Clock
16k Byte ISP Flash
Circuit
Configuration
8k Byte ISP Flash
Program Memory
Program Memory
CIP-51 8051
256 Byte SRAM
512 Byte XRAM
CIP-51 8051
256 Byte SRAM
512 Byte XRAM
Figure 1.3. Si1012 Block Diagram
Figure 1.4. Si1013 Block Diagram
SYSCLK
SYSCLK
Engine
Engine
CRC
CRC
SFR
SFR
Bus
Bus
Rev. 1.0
12/10-bit
75/300 ksps
ADC
Internal
12/10-bit
75/300 ksps
ADC
Internal
VREF
VREF
CP1, CP1A
Timers 0,
CP1, CP1A
Timers 0,
SMBus
Transceiver Control Interface
SMBus
6-bit
IREF
Transceiver Control Interface
Analog Peripherals
UART
1, 2, 3
Analog Peripherals
6-bit
IREF
UART
1, 2, 3
SPI 0
Digital Peripherals
PCA/
WDT
Digital Peripherals
PCA/
SPI 0
WDT
CP0, CP0A
CP0, CP0A
External
External
VREF
VREF
Comparators
Comparators
+
-
+
-
M
U
A
X
M
A
U
X
+
-
Crossbar
Decoder
+
-
Crossbar
Decoder
Priority
Priority
IREF0
IREF0
Sensor
Sensor
VREF
Temp
VDD
GND
VREF
Temp
VDD
GND
(240-960 MHz)
(240-960 MHz)
RF XCVR
RF XCVR
Port I/O
Config
Port I/O
AGC
Modulator
AGC
Config
Modulator
Modem
Digital
Sigma
Digital
OSC
Modem
Delta
Logic
LNA
Digital
Sigma
Digital
PA
OSC
Delta
Logic
LNA
PA
Mixer
PGA
ADC
Mixer
PGA
ADC
15
15
ANALOG &
DIGITAL I/O
TX
RXp
RXn
XIN
XOUT
ANALOG &
DIGITAL I/O
TX
RXp
RXn
XIN
XOUT