SI1014-A-GM Silicon Laboratories Inc, SI1014-A-GM Datasheet - Page 11

• Manufacturer Part Number: SI1014-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1014-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 16kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1869-5

Si1010/1/2/3/4/5
Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 111
Figure 8.1. CIP-51 Block Diagram ......................................................................... 114
Figure 9.1. Si1010/1/2/3/4/5 Memory Map ............................................................ 123
Figure 9.2. Flash Program Memory Map ............................................................... 124
Figure 13.1. Flash Program Memory Map (16 kB and 8 kB devices) .................... 148
Figure 14.1. Si1010/1/2/3/4/5 Power Distribution .................................................. 158
Figure 15.1. CRC0 Block Diagram ........................................................................ 166
Figure 15.2. Bit Reverse Register ......................................................................... 173
Figure 16.1. DC-DC Converter Block Diagram ...................................................... 174
Figure 16.2. DC-DC Converter Configuration Options .......................................... 177
Figure 18.1. Reset Sources ................................................................................... 186
Figure 18.2. Power-Fail Reset Timing Diagram .................................................... 187
Figure 18.3. Power-Fail Reset Timing Diagram .................................................... 188
Figure 19.1. Clocking Sources Block Diagram ...................................................... 194
Figure 19.2. 25 MHz External Crystal Example ..................................................... 196
Figure 20.1. SmaRTClock Block Diagram ............................................................. 203
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 212
Figure 21.1. Port I/O Functional Block Diagram .................................................... 219
Figure 21.2. Port I/O Cell Block Diagram .............................................................. 220
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped .............................. 224
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 225
Figure 22.1. EZRadioPRO Serial Interface Block Diagram ................................... 239
Figure 22.2. SPI Timing ......................................................................................... 241
Figure 22.3. SPI Timing—READ Mode ................................................................. 241
Figure 22.4. SPI Timing—Burst Write Mode ......................................................... 242
Figure 22.5. SPI Timing—Burst Read Mode ......................................................... 242
Figure 22.6. Master Mode Data/Clock Timing ....................................................... 243
Figure 22.7. SPI Master Timing ............................................................................. 248
Figure 23.1. State Machine Diagram ..................................................................... 251
Figure 23.2. TX Timing .......................................................................................... 254
Figure 23.3. RX Timing .......................................................................................... 255
Figure 23.4. Frequency Deviation ......................................................................... 258
Figure 23.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 260
Figure 23.6. FSK vs. GFSK Spectrums ................................................................. 262
Figure 23.7. Direct Synchronous Mode Example .................................................. 265
Figure 23.8. Direct Asynchronous Mode Example ................................................ 265
Figure 23.9. Microcontroller Connections .............................................................. 266
Figure 23.10. PLL Synthesizer Block Diagram ...................................................... 268
Figure 23.11. FIFO Thresholds ............................................................................. 271
Figure 23.12. Packet Structure .............................................................................. 272
Figure 23.13. Multiple Packets in TX Packet Handler ........................................... 273
Figure 23.14. Required RX Packet Structure with Packet Handler Disabled ........ 273
Figure 23.15. Multiple Packets in RX Packet Handler ........................................... 274
Figure 23.16. Multiple Packets in RX with CRC or Header Error .......................... 274
Figure 23.17. Operation of Data Whitening, Manchester Encoding, and CRC ..... 276
Rev. 1.0
11