SI1014-A-GM Silicon Laboratories Inc, SI1014-A-GM Datasheet - Page 182

• Manufacturer Part Number: SI1014-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1014-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 16kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1869-5

Si1010/1/2/3/4/5
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration
SFR Page = 0x0; SFR Address = 0x96
182
Name
Reset
Type
Bit
6:5 CLKDIV[1:0] DC
7
4
3
2
1
0
Bit
AD0CKINV ADC0 Clock Inversion (Clock Invert During Sync).
VDDSLP
CLKSEL
CLKINV
ILIMIT
Name
LPEN
LPEN
R/W
7
0
Low Power Mode Enable.
Enables the dc-dc low power mode which reduces bias currents, reduces peak
inductor current, and increases efficiency for low load currents. Only available on
‘F912 and ‘F902 devices.
0: Low Power Mode Disabled.
1: Low Power Mode Enabled.
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. These bits are ignored when the dc-dc converter is
clocked from its local oscillator.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
Inverts the ADC0 SAR clock derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
DC
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
Peak Current Limit Threshold.
Sets the threshold for the maximum allowed peak inductor current according to
Table 16.1.
VDD
Specifies the power source for VDD_MCU/DC+ in Sleep Mode when the dc-dc con-
verter is enabled.
0: VDD-DC+ connected to VBAT in Sleep Mode.
1: VDD-DC+ is floating in Sleep Mode.
DC
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
R/W
-
-
-
6
0
DC Clock Divider.
DC Converter Clock Invert.
DC Converter Clock Source Select.
CLKDIV[1:0]
-
DC+ Sleep Mode Connection.
R/W
5
0
AD0CKINV
R/W
Rev. 1.0
4
0
Function
CLKINV
R/W
3
0
ILIMIT
R/W
2
0
VDDSLP
R/W
1
0
CLKSEL
R/W
0
0