R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 999
R8A77850BDBGV#RD0Z
Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850BDBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 999 of 1694
- Download datasheet (9Mb)
19.5.6
The display unit (DU) generates a CLAMP signal and DE signal, independent of the DISP signal
indicating the display interval.
The rising-edge start position and high-level width of the CLAMP signal and DE signal, with
reference to the HSYNC signal falling edge, can be set in dot clock units. Figure 19.20 shows the
timing chart.
However, the DE signal is fixed at low level during the vertical blanking interval.
When start position value is 0
When (start position value + high-level width value) exceeds the HSYNC period
DCLKOUT
(output)
HSYNC signal
CLAMP signal/
DE signal
CLAMP signal/
DE signal
CLAMP signal/
DE signal
CLAMP Signal and DE Signal
Figure 19.20 CLAMP Signal and DE Signal
Start position value
+ 1
Starting position value
+ 1
The minimum value of rising position = 1
High-level width value
High-level width value
Rev.1.00 Jan. 10, 2008 Page 967 of 1658
When the HSYNC
signal falls, the
CLAMP signal/DE
signal also falls.
19. Display Unit (DU)
REJ09B0261-0100
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