R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 694

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
(3)
By writing 1 to the SC bit in PCICMD, a wait (stepping) of one clock can be inserted when the
PCIC is driving the AD bus. As a result, the PCIC drives the AD bus with 2 clocks. This function
can be used when the PCI bus load is heavy and the AD bus does not achieve the stipulated logic
level in one clock.
It is recommended to use this function when the PCIC issues configuration transfers in host mode.
Figure 13.27 shows an example of a burst memory write cycle with address stepping. Figure 13.28
shows an example of a target burst read cycle with address stepping.
Rev.1.00 Jan. 10, 2008 Page 662 of 1658
REJ09B0261-0100
Address/Data Stepping Timing
PCICLK
AD[31:0]
PAR
C/BE[3:0]
PCIFRAME
IRDY
DEVSEL
TRDY
Figure 13.27 Master Write Cycle in Host Mode (Burst, with Stepping)
Legend:
Addr: PCI space address
Dn:
nth data
DPn: nth data parity
AP: Address parity
Addr
Com
AP
BE0
D0
DP0
DPn-1
Com: Command
BEn: nth data byte enable
Dn
BEn
DPn