R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 43
R8A77850BDBGV#RD0Z
Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850BDBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Part Number
Manufacturer
Quantity
Price
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Item
Synchronized serial
I/O with FIFO
(SIOF)
Serial protocol
interface (HSPI)
Multimedia card
interface (MMCIF)
Audio codec
interface (HAC)
Features
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Number of channels: One (max.)
Supports full-duplex operation
Separate 64-byte (32 bits x 16) FIFOs for transmission and reception
Supports the input and output of 8-/16-bit monaural and 16-bit
stereophonic audio data
Method of synchronization selectable as frame synchronization pulses or
left/right channel switching
Allows connection of linear, audio, A-law, or μ-Law CODEC chip
Select an on-chip peripheral clock or input on an external pin as base for
the sampling-rate clock
Maximum sampling rate: 48 kHz
On-chip prescaler that uses the on-chip peripheral clock
Number of channels: One (max.)
Supports full-duplex operation
Master/slave mode
Selectable bit rate generated by the on-chip baud-rate generator
Number of channels: One (max.)
Supports a subset of version 3.1 of the multimedia card system
specification
Supports MMC-mode operation
Interfaces with MMCCLK output (transfer clock output), MMCCMD I/O
(command output/response input), and MMCDAT I/O (data I/O) pins
Number of channels: Two (max.)
Digital interface for audio codecs
Supports transfer via slots 1 to 4
Choice of 16- or 20-bit DMA transfer rates for transmission/reception
Supports various sampling rates by adjusting the allocation of data to
slots
Rev.1.00 Jan. 10, 2008 Page 11 of 1658
REJ09B0261-0100
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