R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1631
R8A77850BDBGV#RD0Z
Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850BDBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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32.3.6
Table 32.11 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1)
Conditions: V
Pin
PCICLK
PCIRESET
IDSEL
AD31 to AD0,
C/BE3 to C/BE0,
PCIFRAME,
PAR, IRDY,
TRDY, STOP,
LOCK, PERR,
DEVSEL,
REQ0/REQOUT,
GNT0/GNTIN
REQ1, REQ2,
REQ3, GNT1,
GNT2, GNT3
SERR, INTA,
INTB, INTC,
INTD
PCIC Module Signal Timing
DDQ
= 3.0 to 3.6 V, V
Item
Clock period
Clock pulse width (high)
Clock pulse width (low)
Clock rise time
Clock fall time
Output data delay time
Input setup time
Input hold time
Output data delay time
Tri-state drive delay time t
Tri-state Hi-Z delay time t
Input setup time
Input hold time
Output data delay time
Input setup time
Input hold time
Tri-state drive delay time t
Tri-state Hi-Z delay time t
Input setup time
Input hold time
DD
= 1.1 V, T
Symbol Min.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PCICYC
PCIHIGH
PCIr
PCIf
NCDAD1
PCIVAL
PCISU
PCIH
PCIVAL
PCION
PCIOFF
PCISU
PCIH
PCIVAL
PCISU
PCIH
PCION
PCIOFF
PCISU
PCIH
a
= –40 to 85°C, C
30
11
11
—
—
—
3
1.5
2
2
2
3
1.5
2
3
1.5
—
—
3
1.5
33 MHz
Rev.1.00 Jan. 10, 2008 Page 1599 of 1658
Max. Min.
—
—
—
4
4
10
—
—
10
10
12
—
—
10
—
—
10
12
—
—
L
= 30 pF
15
6
6
—
—
—
3
1.5
2
2
2
3
1.5
2
3
1.5
—
—
3
1.5
66 MHz
32. Electrical Characteristics
Max. Unit
30
—
—
1.5
1.5
10
—
—
6
6
6
—
—
6
—
—
10
12
—
—
REJ09B0261-0100
ns
ns
ns
ns
ns
ns
Figure
32.37
32.38
32.39
32.38
32.39
32.38
32.39
32.38
32.39
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