R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1194

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

23. Serial Peripheral Interface (HSPI)
Rev.1.00 Jan. 10, 2008 Page 1162 of 1658
REJ09B0261-0100
Bit
8
7
6
5
4
3
Bit Name
FFEN
LMSB
CSV
CSA
TFIE
ROIE
0
0
0
Initial
Value
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
FIFO Mode Enable
Enables or disables the FIFO mode. When FIFO mode
is enabled, two 8-entry FIFOs are made available, one
for transmit data and one for receive data. These FIFOs
are read and written via SPTBR and SPRBR,
respectively. When FIFO mode is disabled, the SPTBR
and SPRBR are used directly so new data must be
written to SPTBR and read from SPRBR for each and
every transfer through the HSPI bus. FIFO mode must
be disabled if DMA requests are also to be used to
service SPTBR and SPRBR.
0: FIFO mode disabled
1: FIFO mode enabled
LSB/MSB First Control
0: Data is transmitted and received most significant bit
1: Data is transmitted and received least significant bit
Chip Select Value
Controls the value output as the chip select signal when
the HSPI is a master and manual generation of the chip
select signal has been selected.
0: Chip select output is low.
1: Chip select output is high.
Automatic/Manual Chip Select
0: Chip select output is automatically generated during
1: Chip select output is manually controlled, with its
Transmit Complete Interrupt Enable
0: Transmit complete interrupt disabled
1: Transmit complete interrupt enabled
Receive Overrun Occurred/Warning Interrupt Enable
0: Receive overrun occurred/warning interrupt disabled
1: Receive overrun occurred/warning interrupt enabled
(MSB) first.
(LSB) first.
data transfer.
value being determined by the CSV bit.