R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 526
R8A77850BDBGV#RD0Z
Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850BDBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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12. DDR2-SDRAM Interface (DBSC2)
Note: Writing to this register should be performed only when the following conditions are met.
Rev.1.00 Jan. 10, 2008 Page 494 of 1658
REJ09B0261-0100
Bit
2 to 0
•
•
Bit Name
TWR0
TWR2 to
When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.).
When automatic issue of auto-refresh is disabled (when the ARFEN bit in the
DBRFCNT0 register is cleared to 0.).
Initial
Value
001
R/W
R/W
Description
tWR (write recovery period) Setting Bits
These bits set the write recovery minimum period
constraint. These bits should be set according to the
DDR2-SDRAM specifications. The number of cycles is
the number of DDR clock cycles.
000: Setting prohibit (If specified, correct operation
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: Setting prohibit (If specified, correct operation
111: Setting prohibit (If specified, correct operation
:
cannot be guaranteed.)
cannot be guaranteed.)
cannot be guaranteed.)
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