R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 319

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(7)
INTMSK2 is a 32-bit readable and conditionally writable register that sets masking for IRL
interrupt requests for input level pattern on the IRL pins. To clear the mask setting for the
interrupt, write 1 to the corresponding bit in INTMSKCLR2. Writing 0 to the bits in INTMSK2
has no effect. By reading this register once after writing to this register or after clearing the mask
by setting IMTMSKCLR2, the time length necessary for reflecting the register value can be
assured (the value read is reflected to the mask status).
INTMSK2 settings are valid when the IRQ/IRL3 to IRQ/IRL0 pins or IRQ/IRL7 to IRQ/IRL4
pins are used for encoded IRL interrupt inputs, and the corresponding IRL interrupt is not masked
by INTMSK1.
Initial value:
Initial value:
Bit
31
30
29
28
27
R/W:
R/W:
Interrupt Mask Register 2 (INTMSK2)
Bit:
Bit:
Name
IM015
IM014
IM013
IM012
IM011
IM115 IM114
IM015 IM014
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
IM013
IM113
R/W
R/W
29
13
0
0
Initial
Value
0
0
0
0
0
IM012
IM112
R/W
R/W
28
12
0
0
IM011
IM111
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
27
11
0
0
IM010
IM110
R/W
R/W
26
10
0
0
Description
Masks the interrupt source
of IRL3 to IRL0 = LLLL
(H'0).
Masks the interrupt source
of IRL3 to IRL0 = LLLH
(H'1).
Masks the interrupt source
of IRL3 to IRL0 = LLHL
(H'2).
Masks the interrupt source
of IRL3 to IRL0 = LLHH
(H'3).
Masks the interrupt source
of IRL3 to IRL0 = LHLL
(H'4).
IM009
IM109
R/W
R/W
25
0
9
0
IM008
IM108
R/W
R/W
24
0
8
0
IM007
IM107
R/W
R/W
23
0
7
0
IM006
IM106
Rev.1.00 Jan. 10, 2008 Page 287 of 1658
R/W
R/W
22
0
6
0
IM005
IM105
R/W
R/W
21
0
5
0
10. Interrupt Controller (INTC)
IM004
IM104
[When read]
0: The interrupt is
1: The interrupt is
[When written]
0: No effect
1: Masks the interrupt
R/W
R/W
20
0
4
0
accepted.
masked.
IM003
IM103
R/W
R/W
19
0
3
0
REJ09B0261-0100
IM002
IM102
R/W
R/W
18
0
2
0
IM001
IM101
R/W
R/W
17
0
1
0
16
⎯
⎯
R
R
0
0
0