R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1190
R8A77850BDBGV#RD0Z
Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850BDBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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23. Serial Peripheral Interface (HSPI)
23.3.2
SPSR is a 32-bit readable/writable register. Through the status flags in SPSR, it can be confirmed
whether or not the system is correctly operating. If the ROIE bit in SPSCR is set to 1, an interrupt
request is generated due to the occurrence of the receive buffer overrun error or the warning of the
receive buffer overrun error. When the TFIE bit in SPSCR is set to 1, an interrupt request is
generated by the transmit complete status flag. If the appropriate enable bit in SPSCR is set to 1,
an interrupt request is generated due to the receive FIFO halfway, receive FIFO full, transmit
FIFO empty, or transmit FIFO halfway flag. If the RNIE bit in SPSCR is set to 1, an interrupt
request is generated when the receive FIFO is not empty.
Rev.1.00 Jan. 10, 2008 Page 1158 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 11 ⎯
10
9
R/W:
R/W:
Bit:
Bit:
Status Register (SPSR)
Bit Name
TXFU
TXHA
31
15
—
—
—
—
R
R
30
—
—
14
—
—
R
R
Initial
Value
Undefined R
0
0
29
—
—
13
—
—
R
R
28
12
—
—
—
—
R
R
27
11
—
—
—
—
R
R
R/W
R
R
TXFU
26
10
—
—
R
R
0
Description
Reserved
These bits are always read as an undefined value. The
write value should always be 0.
Transmit FIFO Full Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the transmit FIFO is full of bytes for
transmission and cannot accept any more. It is cleared
to 0 when data is transmitted from the transmit FIFO to
the HSPI bus.
Transmit FIFO Halfway Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the transmit FIFO reaches the halfway
point, that is, it has four bytes of data and free space for
four bytes of data. It is cleared to 0 when more data is
written to the transmit FIFO. It remains set to 1 until
cleared to 0 even if data stored in the FIFO becomes
less than four bytes (halfway point).
If TXHA = 1 and THIE = 1, an interrupt is generated.
TXHA
25
—
—
R
R
9
0
TXEM
24
—
—
R
R
8
1
RXFU
23
—
—
R
R
7
0
RXHA
22
—
—
R
R
6
0
RXEM
21
—
—
R
R
5
1
RXOO
R/W*
20
—
—
R
4
0
RXOW
R/W*
19
—
—
R
3
0
RXFL
18
—
—
R
R
2
0
TXFN
17
—
—
R
R
1
0
TXFL
16
—
—
R
R
0
0
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