R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 330

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
10.3.2
(1)
USERIMASK is a 32-bit readable and conditionally writable register that sets the acceptable
interrupt level. This register is allocated to the 64-Kbyte page that the other registers in the INTC
are not allocated. Therefore, only this register can be set to be accessible in user mode by changing
the address to area 7 address through the MMU.
The interrupts that the level is lower than the level set in the UIMASK bits are masked. When H'F
is set in the UIMASK bit, all interrupts other than the NMI are masked.
The interrupts that the level is higher than the level set in the UIMASK bits are accepted under the
following conditions. The corresponding interrupt mask bit in the interrupt mask register is cleared
to 0 (the interrupt is enabled). The IMASK bit in SR is set lower than its interrupt level.
The value of the UIMASK bit does not change even if an interrupt is accepted.
USERIMASK is initialized to H'0000 0000 (all interrupts are enabled) by a power-on reset or
manual reset.
To prevent incorrect writing, this register should not be written to unless bits 31 to 24 are set to
H'A5.
Rev.1.00 Jan. 10, 2008 Page 298 of 1658
REJ09B0261-0100
Initial value:
Initial value:
R/W:
R/W:
User Interrupt Mask Level Setting Register (USERIMASK)
Bit:
Bit:
User Mode Interrupt Disable Function
R/W
31
15
⎯
R
0
0
R/W
30
14
⎯
R
0
0
R/W
29
13
⎯
R
Code for writing (H'A5)
0
0
R/W
28
12
⎯
R
0
0
R/W
27
11
⎯
R
0
0
R/W
26
10
⎯
R
0
0
R/W
25
⎯
R
0
9
0
R/W
24
⎯
R
0
8
0
R/W
23
⎯
R
0
7
0
R/W
22
⎯
UIMASK
R
0
6
0
R/W
21
⎯
R
0
5
0
R/W
20
⎯
R
0
4
0
19
⎯
⎯
R
R
0
3
0
18
⎯
⎯
R
R
0
2
0
17
⎯
⎯
R
R
0
1
0
16
⎯
⎯
R
R
0
0
0