R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1034

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20. Graphics Data Translation Accelerator (GDTA)
• mbcol: Row position in macroblock units (number of macroblocks)
• mbrow: Column position in macroblock units (number of macroblocks)
• Forward_Recon_down: Past-frame vertical-direction vector (half-pixel units)
• Forward_Recon_right: Past-frame horizontal-direction vector (half-pixel units)
• Back_Recon_down: Future-frame vertical-direction vector (half-pixel units)
• Back_Recon_right: Future-frame horizontal-direction vector (half-pixel units)
• Buffer RAM pointer: Pointer to the buffer RAM 1 in use (RAM 1 address storing IDCT data)
Notes on MC Command FIFO Register (MCCF) Settings:
1. Buffer RAM pointers should point to addresses on 4-byte boundaries. If not, the lower address
2. When setting values in this register in succession, the MC module is able to receive the next
3. Four commands can be received. If the next command is written when the command FIFO is
4. Specify the RAM 1 pointer even when the cbp is set to 6'h00. The specified address should be
5. In intra macroblock processing mode, the output data values are not guaranteed if the cbp is set
Rev.1.00 Jan. 10, 2008 Page 1002 of 1658
REJ09B0261-0100
⎯ Bit 26: Indicates whether or not the V IDCT data exists (0: IDCT data is invalid, 1: IDCT
is regarded as 0.
command while the MC_CFF bit in MCSR is 0. To perform processing by changing the
command alone, just set the new command in this register.
full, the commands stored in the command FIFO are retained and the next command is
ignored.
H'FE42_0000.
to a value other than 6'h3F.
data is valid)