R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1153

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
7 to 5
4 to 0
Bit Name
RFWM[2:0] 000
RFUA[4:0]
Initial
Value
00000
R/W
R/W
R
Description
Receive FIFO Watermark
000: Issue a transfer request when 1 stage or more of
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 4 or more stages of
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 12 or more stages
111: Issue a transfer request when 16 stages of the
•
•
Receive FIFO Usable Area
These bits indicate the number of words that can be
transferred by the CPU or DMAC as B'00000 (empty) to
B'10000 (full).
A transfer request to the receive FIFO is issued by
the RDREQE bit in SISTR.
The receive FIFO is always used as 16 stages of
the FIFO regardless of these bit settings.
the receive FIFO are valid.
the receive FIFO are valid.
the receive FIFO are valid.
of the receive FIFO are valid.
receive FIFO are valid.
Rev.1.00 Jan. 10, 2008 Page 1121 of 1658
22. Serial I/O with FIFO (SIOF)
REJ09B0261-0100