R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1109

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 21.8 shows a sample SCIF initialization flowchart.
clear TFCL and RFCL bits to 0
SCSCR to 1, and set TIE, RIE,
in SCSCR (leaving TIE, RIE,
TE, and RE bits cleared to 0)
Set TFCL and RFCL bits in
Set RTRG1 and RTRG0,
MCE bits in SCFCR, and
Set CKE1 and CKE0 bits
TTRG1 and TTRG0, and
Clear TE and RE bits in
Set data transfer format
1-bit interval elapsed?
Set TE and RE bits in
Set value in SCBRR
Start of initialization
End of initialization
Figure 21.8 Sample SCIF Initialization Flowchart
and REIE bits
SCSCR to 0
SCFCR to 1
in SCSMR
Yes
Wait
No
[1]
[2]
[3]
[4]
21. Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Set the data transfer format in
SCSMR.
Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
Wait at least one bit interval, then
set the TE bit or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits.
Setting the TE and RE bits
enables the SCIF_TXD and
SCIF_RXD pins to be used.
When transmitting, the SCIF goes
to the mark state; when receiving,
it goes to the idle state, waiting for
a start bit.
Rev.1.00 Jan. 10, 2008 Page 1077 of 1658
REJ09B0261-0100