R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 719

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
11 to 8
7
6
5
4, 3
Bit Name
RS[3:0]
DL
DS
TB
TS[1:0]
Initial
Value
0000
0
0
0
00
R/W
R/W
R/W
R/W
R/W
R/W
Descriptions
Resource Select 3 to 0
Specify the transfer request source. To change the
transfer request source, the DMA enable (DE) bit
should be cleared to 0.
0000: External request, or dual address mode
0100: Auto-request
1000: On-chip peripheral module request
Other than above: Setting prohibited
Note: External request specification is valid in only
DREQ Level and DREQ Edge Select
Specify the detecting method of the DREQ input and
the detecting level.
These bits are valid in only CHCR0 to CHCR3. Even in
channels 0 to 3, if the transfer request source is
specified as an on-chip peripheral module or if an auto-
request is specified, these bits are invalid.
00: DREQ detected in low level (DREQ)
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
Transfer Bus Mode
Specifies the bus mode for DMA transfers.
0: Cycle steal mode
1: Burst mode
Select cycle steal mode when the on-chip peripheral
module requests are specified. This bit can be set to 0
or 1 only for channels 0 to 5.
For channels 6 to 11, this bit cannot be set to 1. The
write value should always be 0.
DMA Transfer Size Specification
See the description of TS2 (bit 20).
CHCR0 to CHCR3. The external request cannot
be specified in CHCR4 to CHCR11.
Selected by DMA extended resource selector
(DMARS0 to DMARS5)
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 687 of 1658
REJ09B0261-0100