R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 19

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.5 DMAC Interrupt Sources ................................................................................................... 729
14.6 Usage Notes ....................................................................................................................... 730
Section 15 Clock Pulse Generator (CPG)
15.1 Features.............................................................................................................................. 733
15.2 Input/Output Pins ............................................................................................................... 736
15.3 Clock Operating Modes ..................................................................................................... 737
15.4 Register Descriptions ......................................................................................................... 739
15.5 Calculating the Frequency ................................................................................................. 748
15.6 How to Change the Frequency........................................................................................... 749
15.7 Notes on Designing Board ................................................................................................. 756
Section 16 Watchdog Timer and Reset (WDT)
16.1 Features.............................................................................................................................. 759
16.2 Input/Output Pins ............................................................................................................... 761
16.3 Register Descriptions ......................................................................................................... 762
16.4 Operation ........................................................................................................................... 769
14.4.2
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.6.1
14.6.2
14.6.3
14.6.4
14.6.5
14.6.6
15.4.1
15.4.2
15.4.3
15.4.4
15.6.1
15.6.2
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
Channel Priority.................................................................................................. 706
DMA Transfer Types.......................................................................................... 709
DMA Transfer Flow ........................................................................................... 717
Repeat Mode Transfer ........................................................................................ 719
Reload Mode Transfer ........................................................................................ 720
DREQ Pin Sampling Timing .............................................................................. 721
Stopping Modules and Changing Frequency ...................................................... 730
Address Error...................................................................................................... 730
NMI Interrupt...................................................................................................... 730
Burst Mode Transfer........................................................................................... 730
Divided-Up DACK Output................................................................................. 730
DACK/DREQ Setting......................................................................................... 731
Frequency Control Register 0 (FRQCR0) .......................................................... 741
Frequency Control Register 1 (FRQCR1) .......................................................... 742
Frequency Display Register 1 (FRQMR1) ......................................................... 745
PLL Control Register (PLLCR).......................................................................... 747
Changing the Frequency of Clocks Other than the Bus Clock ........................... 749
Changing the Bus Clock Frequency ................................................................... 749
Watchdog Timer Stop Time Register (WDTST) ................................................ 763
Watchdog Timer Control/Status Register (WDTCSR)....................................... 764
Watchdog Timer Base Stop Time Register (WDTBST)..................................... 766
Watchdog Timer Counter (WDTCNT)............................................................... 767
Watchdog Timer Base Counter (WDTBCNT) ................................................... 768
..................................................................... 733
........................................................... 759
Rev.1.00 Jan. 10, 2008 Page xvii of xxx
REJ09B0261-0100