R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1116

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ADBGV#RD0Z

Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ADBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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21. Serial Communication Interface with FIFO (SCIF)
5. When modem control is enabled, the SCIF_RTS signal is output when SCFRDR is empty.
Figure 21.14 shows an example of the operation when modem control is used.
Rev.1.00 Jan. 10, 2008 Page 1084 of 1658
REJ09B0261-0100
When SCIF_RTS is 0, reception is possible. When SCIF_RTS is 1, this indicates that
SCFRDR contains bytes of data equal to or more than the SCIF_RTS output active trigger
count. The SCIF_RTS output active trigger value is specified by bits 10 to 8 in SCFCR. For
details, see section 21.3.9, FIFO Control Register n (SCFCR). In addition, SCIF_RTS is also 1
when the RE bit in SCSCR is cleared to 0.
SCIF_RXD
SCIF_RTS
Serial data
Figure 21.14 Example of Operation Using Modem Control (SCIF_RTS)
Start
bit
0
D0
D1 D2
(Only in Channels 1 and 2)
D7 0/1 1
Parity
bit
Stop
bit
Start
bit
0

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